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Features
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High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion Very effective associated Physical synthesis/optimization Flow From 45K Gates up to 1000K Gates Supported From 55Kbit to 847Kbit DPRAM Compatible with Xilinx and Altera Latest FPGA's Pin-count: Over 700 pins VDD 1.8V +/- 0.15V for core; 1.8V, 2.5V, 3.3V for Periphery Any Pin-out Matched Full Range of Packages: PQFP/TQFP/VQFP, BGA/FLBGA, PGA/PPGA, QFN, CS Available in Commercial, Industrial and Military Grades 0.18 um Drawn CMOS, 5 Metal Layers Library Optimised for best Synthesis, Place & route and Testability Generation (ATPG) High system clock Skew Control 250Mhz system clock, up to 400Mhz for local clock Power on Reset, PLL, Multiplier Standard 3, 6, 12, 24 mA I/Os LVCMOS, LVTTL, GTL, HSTL, LVPECL, PCI & LVDS Interfaces High Noise & EMC Immunity Thick Oxide periphery Allowing Interface with 2.5V and 3.3V Environments
0.18 um ULC Series with Embedded DPRAM ATU18
Description
The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs. It supports within one ULC 55Kbits to 847Kbits DPRAM and 45Kgates to 1000 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA. Metal level customisation allows a DPRAM blocks compatibility with Xilinx(R) or Altera(R) blocks. Devices are implemented in high-performance 0.18 um CMOS technology to improve the design frequency and reach 250Mhz typical application and local clock up to 400Mhz. The architecture of the ATU18 series is dedicated for efficient conversion of latest CPLD and FPGA device types with higher IO count. A compact RAM cell and a large number of available gates allow the implementation of memories compatible with FPGA RAM, as well as JTAG boundary-scan and scan-path testing. Conversion to the ATU18 series of ULC provides a significant reduction of the operating power when compared to the original PLD or FPGA. The ATU18 series has a very low standby consumption, less than 0.145 nA/gate typically at commercial temperature. Operating consumption is a strict function of clock frequency, which typically results in a significant power reduction depending on the device being compared. For a NAND2 cell the dynamic power consumption is 0.124uW/MHz at 1.8V.
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The ATU18 series provide several options for output buffers, including a variety of drive levels up to 24mA. Schmitt trigger inputs are also available. A number of techniques are used to improve noise immunity and to reduce EMC emissions, including several independent power supply buses and internal decoupling for isolation. The ATU18 series are designed to allow conversion of high performance 1.8V devices. Support of mixed supply conversions is also possible, allowing optimal trade-offs between speed and power consumption.
Array Organization
Table 1. Matrices
Part Number ATU18_680 ATU18_600 ATU18_484 ATU18_432 ATU18_352 ATU18_304 ATU18_256 ATU18_160 Max Pads 680 600 484 432 352 304 256 160 Gates 1000K 720K 486K 330K 276K 171K 111K 45K DPRAM bits 847K 700K 460K 350K 221K 183K 147K 55K PLL 4 4 2 2 2 2 2 1
Architecture
The ATMEL 0.18um matrices allow conversions of designs being developed on Altera/ApexApexTMII Stratix(R) CycloneTM or Xilinx/VirtexTM, SpartanTM and CoolRunnerTM families. Each matrix contains configurable memory DPRAM blocks, PLLs (from 2 to 4) and Power-on-Reset. It can also integrate a 1.8V regulator from 3.3V supply if no available 1.8V on the board. The associated Physical synthesis/optimization flow contributes to achieve high speed designs, even improving drastically the application frequency and power consumption.
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ATU18
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ATU18
Figure 1. Atmel 0.18um matrix supply rings configurable DPRAMs core logic area PLLs configurable IO pads
DPRAM Description
For flexibility, the embedded DPRAMs blocks, using an ATMEL memory configuration tool, are configured at customization Metal levels, in order to match behaviour and format of Xilinx or Altera memories.
Figure 1. ATMEL Memory Configuration Tool
For test in production, a bist is systematically inserted, without degrading the performances. The memories will be then automatically tested to provide high reliability.
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Table 2. Dual Port Mode Configurations
Memory area 576k bits Port A Port B 64kx9 64kx9 64kx9 32kx18 64kx9 16kx36 64kx9 8Kx72 16kx1 16kx1 16kx1 8kx2 Memory Area 18K bits 16kx1 4kx4 16kx1 2kx9 16kx1 1kx8 16kx1 512x36
Port A Port B
32kx18 32kx18
32kx18 16kx36
32kx18 8kx72
8kx2 8kx2
8kx2 4kx4
8kx2 2kx9
8kx2 1kx18
8kx2 512x36
Port A Port B
16kx36 16kx36
16kx36 8kx72
4kx4 4kx4
4kx4 2kx9
4kx4 1kx18
4kx4 512x36
Port A Port B
8kx72 8kx72
2kx9 2kx9
2kx9 1kx18
2kx9 512x36
Port A Port B
4Kx144 4Kx144
1kx18 1kx18
1kx18 512x36
Port A Port B
512x36 512x36
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ATU18
I/O Buffer Interfacing
I/O Flexibility All I/O buffers at the periphery may be configured as input, output, bi-directional and oscillator. The IO power rings can be modified to allow clusterization (i.e. cluster at 1.8V cluster at 3.3V). When core supply differs from periphery supply, level shifters are available in IO buffers, for example in the following conditions: 3.3V I/O -> 1.8V core, 2.5V I/O->1.8V core.
Each LVTTL, LVCMOS, or Schmitt Trigger input can be programmed with or without a pull up or pull down resistor or bus keeper. The Standard IO supported are given in table 3. Fast Output Buffer are able to drive 3 to 24mA at 3.3V according to the chosen option. (higher drive is achievable using two adjacent pads). Table 3. Standard IO Supported
Standard IO LVTTL LVCMOS PCI33 PCI66 GTL GTL+ HSTL I, II, III, IV SSTL2 I, II SSTL3 LVPECL LVDS Comment 3.3V ( 3 to 24 mA) 1.8V/2.5V/3.3V ( 3 to 24 mA) 3.3V 3.3V 3.3V 3.3V input only input only input only input only 3.3V
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PLL Description
ATMEL PLL is available for a large range of frequencies. It has an internal filter and no external component is necessary. Programming at customization level allows to choose between four ranges of VCO frequency as shown in the table below:
FreqSelect1 0 0 1 1 FreqSlect0 0 1 0 1 VCO Frequency 66-90Mhz 90-160Mhz 155-300Mhz 280-500Mhz
Different outputs are also available, to ensure a wide variety of use. The drawing below shows the IOs of the PLL.
VccPLL
FREQIN DIVOUT ENPLL FREQSELECT(1:0) ICP(1:0) SYNC VCOIN ENVCOIN SC1 SC2 SR1 SR2
OUT0 OUT90 OUT180 OUT270
OUTX0 OUTX180
OUT1 OUT2
LCK
VssPLL
Table 4. Pin Description
Pin Name FREQIN DIVOUT FREQSELECT(1:0) SC2,SC1 ICP(1:0) TYPE digital digital digital digital digital I/O I I I I I Function Reference input frequency Feedback input frequency VCO frequency range select internal filter value select Charge pump current select
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ATU18
Table 4. Pin Description
Pin Name SR1, SR2 SYNC VCOIN ENVCOIN OUT0 OUT90 OUT180 TYPE digital digital analog digital digital digital digital I/O I I I I O O O Function internal filter value select synchronization mode select VCO external input VCO external input select 0 degree phase shift of VCO freq divided by 4 90 degree phase shift of VCO freq divided by 4 180 degree phase shift of VCO freq divided by 4 270 degree phase shift of VCO freq divided by 4 0 degree phase shift of VCO freq divided by 2 180 degree phase shift of VCO freq divided by 2 VCO output delayed VCO output from OUT1 lock output VDD 1.8V pin VSS pin
OUT270 OUTX0 OUTX180 OUT1 OUT2 LCK VCCPLL VSSPLL
digital digital digital digital digital digital power power
O O O O O O I I
VCO FREQUENCY 66-90Mhz 90-160Mhz 155-300Mhz 280-500Mhz
OUT1,OUT2 66-90Mhz 90-160Mhz 155-300Mhz 280-500Mhz
OUTX0, OUTX180 33-45Mhz 45-80Mhz 77.5-150Mhz 140-250Mhz
OUT[0,90,180,270] 16.5-22.5Mhz 22.5-40Mhz 38-75Mhz 70-125Mhz
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PLL Applications
ATMEL PLL is configurable to support applications as: - Clock tree delay reduction - Zero delay buffer - Phase shift - Frequency synthesis
Clock Tree Delay Reduction
Typically, clock tree synthesis is able to build a very performant clock tree (for example: 0.15ns of skew for a clock tree connected to 25000 Flipflops). For that, however, the clock tree latency is increased during clock tree insertion. To satisfy Tco propagation delay, the PLL can be used to reduce and even remove the clock tree delay.
Frequency Synthesis
By adding dividers on input clock and feedback clock, the PLL can be used to multiply the input frequency by a factor determined by the user, as illustrated below: Figure 3. PLL Frequency Synthesis CLKin
%M
freqin Phase divout comp
Charge Pump
VCO
PLL
%2
outx0
CLKout
%N
For example, with a 32Mhz input clock, to generate a 160 Mhz frequency clock on the output outx0, it is necessary to set the input clock divider M to 1 and the feed-back clock divider N to 10.
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ATU18
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ATU18
Atmel Flow
With 0.18um technology, ATMEL has introduced Physical synthesis to optimize design speed. Physical synthesis takes into account the placement and the routing of the cells, and the optimization in incremental mode can be done on the full design or only partially. The result is that ATMEL has faster chips, using the same RTL code. Less iterations are necessary and the timings target is quickly reached.
Customer Pinout
Customer RTL Code SYNTHESIS Timing , Power OPT ATMEL NETLIST SCAN, JTAG, BIST NETLIST for Layout
Customer Timing constraints
ATMEL Bonding diagram
Formal Proof
PHYSICAL SYNTHESIS
Placement
Clock Tree synthesis
Route
Post layout Simulations, Timing & power Analysis
DRC - LVS
TAPE OUT
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ATU18 Packages
The following packages are supported:
ATU18_680 100 TQFP 144 TQFP 100 PQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP 100 FLBGA 144 FLBGA 256 FLBGA 324 FLBGA 456 FLBGA 484 FLBGA 556 FLBGA 672 FLBGA 676 FLBGA 680 FLBGA 780 FLBGA 860 FLBGA 900 FLBGA 1020 FLBGA 1156 FLBGA 1508 FLBGA 225 BGA 256 BGA 313 BGA 329 BGA 352 BGA 356 BGA 432 BGA 560 SBGA 600 SBGA 652 SBGA ATU18_600 ATU18_484 ATU18_432 ATU18_352 ATU18_304 ATU18_256 ATU18_160
gray cells : supported package configuration Remark: Other package and package/matrix configurations can be supported upon request 10
ATU18
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ATU18
Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature Commercial..........................................................0 to 70C Industrial............................................................-40 to 85C Military...............................................................-55 to 125C Max Supply Core Voltage (VDD)..........................1.95 V Max Supply Periphery Voltage (VCC)...................3.6V 3.3V Tolerant/Compliant.....................................Vcc +0.3V Pad pullup resistor.............................................100Kohms Pad pulldown resistor........................................100Kohms Output buffer drive range....................................3 to 24 mA leakage current at Temp=25C..............................0.145nA/gate NAND2 dynamic power consumption......0.124uW/MHz at 1.8V Storage Temperature...........................................-65 to 150C *NOTICE: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
PLL Specifications
Operating Modes Clock tree reduction Zero delay buffer Phase shift Frequency synthesis
VCO range ..........................................66Mhz to 500Mhz OUT1, OUT2 output range..................66Mhz to 500 Mhz OUTX0, OUTX180 ouput range............33Mhz to 250 Mhz OUT0,90,180,270 output range...........16.5Mhz to 125Mhz VDDPLL supply ...................................1.8V +- 10%
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